IBM Unveils Sub-1 Nanometer Chip Technology

IBM is unveiling a major semiconductor breakthrough with the introduction of the world’s first sub-1 nanometer (nm) chip technology, featuring a revolutionary transistor architecture at the 0.7 nm, or 7 angstrom node.

According to IBM, the achievement marks a landmark moment for an industry facing the physical limits of traditional chip scaling. Semiconductors play critical roles in everything from computing, to appliances, to communication devices, transportation systems, and critical infrastructure.

IBM’s new sub-1 nm chip packs nearly 100 billion transistors onto a chip the size of a fingernail, nearly twice the density of IBM’s 2 nm chip, unveiled in 2021.

Enabled by a series of structural and material innovations, including IBM’s groundbreaking three-dimensional nanostack architecture, the technology demonstrates how continued gains in performance and efficiency remain possible even as chip features approach atomic dimensions, said IBM.

“IBM’s latest chip breakthrough marks a landmark moment in computing, pushing technology beyond the nanometer era to the scale of atoms. With our new nanostack architecture, we’re not just making smaller transistors, we’re reinventing how chips are built to deliver dramatically more power and energy efficiency,” said Jay Gambetta, director of IBM research and IBM fellow. “This industry-first innovation continues IBM’s legacy of leading in next-generation technologies and sets the foundation for the next era of computing.

To produce this chip, IBM researchers developed an entirely new transistor architecture, called “nanostack,” the industry’s first known three-dimensional, nanosheet-based design.

Nanostack represents a major advance beyond nanosheet technology, the industry’s current leading-edge architecture, invented by IBM. The nanostack design vertically stacks and staggers transistors, taking advantage of 3D sequential integration to pack more transistors onto a chip. The design also unlocks the use of different material combinations within each stacked layer, optimizing performance and power efficiency of each transistor independent of the other, said IBM.

IBM’s nanostack architecture was experimentally validated through ultra-thin dielectric bonding in CMOS integration, demonstration of dual-channel engineering capability, and functional CMOS inverter operation with expected switching performance. Together, these results confirm the nanostack technology can be physically built and supports real computation.

This breakthrough is the latest testament to IBM as a leader in semiconductor R&D. IBM has led the world in developing the chips that power computing systems for decades, from early semiconductors in the 1960s to the world’s first 2 nm node chip. IBM continues to innovate at the cutting edge of silicon, AI hardware, logic, and quantum processors developed to power the future of computing, said the company.

IBM and its partners conduct this work at a semiconductor research facility in Albany, New York, which will soon be home to a High Numerical Aperture Extreme Ultraviolet (High NA EUV) lithography tool, essential for the future of logic scaling.

 Developed by ASML, this technology enables ultra-precise circuit printing, supporting the creation of smaller, more powerful chips. IBM and partners including Lam Research Corp., Tokyo Electron, and SCREEN Semiconductor Solutions, Ltd. have been working together to develop new High NA EUV processes and tools that have already yielded working devices.